A major trend in the electronic community is to scale to smaller sizes while integrating more functions onto a single integrated circuit. This demands a process that can offer both high performance analog and digital capabilities, e.g. a BiCMOS process. Some advantages of such a process are increased performance, reduced system size and improved system reliability. One result of the trend to higher integration is that supply potentials must also decrease,. However, in many analog applications, existing restraints force the supply potentials to remain at values greater than 5, 10 or 20 volts. In some cases the circuits may be required to withstand a bias of 30 volts or greater.
A second trend in the electronic community is toward a system approach for circuit design. This approach requires the use of many standard cell designs in the design and production of BiCMOS devices. This allows sub-circuits that have been characterized and placed in a library to be used in many designs.
The process for many bipolar circuits developed for a particular operating voltage must be changed, however, in order for the operating voltage to be increased. This requirement is in conflict with the standard cell design approach, since changing the process requires new cell design and recharacterization.
The primary measure of the potential operating voltage of a bipolar NPN transistor is the breakdown voltage between the collector and emitter with the base opened (BVceo). Typically it is this breakdown voltage that limits the operating voltage. In order to increase the operating voltage of the transistor and thereby t, he circuit, it becomes necessary to increase the BVceo.
One technique for accomplishing this is to increase the epitaxial thickness that is deposited in the bipolar process. Such a technique is described in a related pending application, TI-13876, filed Sep. 25, 1989, under Ser. No. 07/411,782, which is incorporated herein by reference thereto. This approach involves increasing the epitaxial thickness without modifying the Nwell that is used for the lower voltage CMOS and bipolar components. Instead of driving the Nwell deeper to meet the up-diffusing N+BL, an additional phosphorus implant is incorporated in the N+BL. This phosphorus diffuses faster than the antimony N+BL. This results in the phosphorus bridging the gap between the unmodified Nwell and the N+BL. This structure is depicted in FIG. 1a along with a doping profile through the higher-voltage NPN transistor base-collector regions (FIG. 1b). Indicated on the doping profile is the phosphorous n-profile and the Nwell profile. These two profiles combine to form the net phosphorous doping profile while allowing the n+ buried layer (Sb) to meet with the Nwell.
Since the thickness of the epitaxial layer is increased, the operating voltage of the circuit also increases due to an increase in the BVcbo(bulk) term in the relationship: ##EQU1## Here, BVcbo(bulk) is the thickness-limited breakdown voltage between the N+ buried collector and base with the emitter open that occurs at the planar or bottom of the base-collector junction. This portion of the collector-base junction is where the: current flows in a vertical bipolar transistor. The planar breakdown of this portion is independent of the radius of curvature of the junction. The hFE is the common-emitter current gain of the transistor, and n is a process dependent empirical parameter typically on the order of 3 to 6.
While this approach does address the issue of not altering the design rules of the lower voltage CMOS and bipolar structures, it does require an increase in the epitaxial thickness. This increase in the epitaxial thickness results in additional collector series resistance. In the case of bipolar transistors, especially high current transistors, this additional series resistance can be detrimental since it degrades the current carrying capability of the device at a particular voltage. It is not possible to selectively build higher voltage structures with this technique since the epitaxial thickness can not be selectively increased in some areas of the circuit while remaining unchanged in others. Therefore, all bipolar transistors, higher voltage and lower voltage, are affected in terms of their series resistance. Therefore, while the lower voltage design rules are unaffected, the circuit models of the lower voltage circuits need to be adjusted for this series resistance. It may be possible that, after making the alteration to the lower voltage circuit model, the circuit performance is detrimentally affected.
Another approach to increase BVceo is to decrease the hFE of the devices. This, however, is typically not a practical solution since the trade-off between operating voltage and the gain of the device is not desirable due to degraded performance of the transistor.
The BVceo of the NPN bipolar transistor can be increased if the n+ buried layer is removed or its doping level greatly reduced due to the increase in the thickness-limited BVcbo(bulk). However, high collector series resistance and reduced NPN performance would result.
A disadvantage of increasing the epitaxial thickness in a typical prior art buried collector bipolar process is that as the epitaxial thickness is increased, the need exists to diffuse the p-type isolation a greater distance. This also produces an increase in the lateral diffusion of the isolation, thereby increasing design rules in terms of the distance between each diffusion and isolation region. Thus, the transistor size would be scaled to larger dimensions. This is depicted in FIGS. 2(a) and 2(b). As can be seen when comparing the two structures, several spacings have been affected by the increased diffusion necessary to obtain adequate isolation for the thicker epitaxial layer. An increase in the design rules of the low voltage device as well as the high voltage device would be required because of the increased lateral diffusion.
Since bipolar-oriented BiCMOS processes suffer from poor packing densities due to the use of thicker epitaxial layers and the need for deep p+ isolation similar to that shown in FIG. 2(b), many advanced BiCMOS processes are CMOS-oriented, where the CMOS process is Nwell based (i.e. Nwell BiCMOS process). The Nwell BiCMOS process allows the NPN collector region to be self-isolating with the p-epitaxial layer acting as the isolation region. Also, Nwell CMOS processes are commonly used in analog and digital applications. Therefore, this choice of starting process can minimize the amount of device re-characterization needed after merging bipolar components.
In order to increase the operating voltage of the bipolar transistors in an Nwell BiCMOS process, a similar approach could be taken to increase the epitaxial layer, resulting in a higher-voltage Nwell BiCMOS process. FIG. 3(a) shows a standard BiCMOS cross-section, while FIG. 3(b) shows the same type of structure with a higher voltage capability resulting from a thicker epitaxial layer. As in the bipolar process, if the epitaxial thickness is increased, the Nwell must be driven deeper into the epitaxial layer in order to meet the up diffusing n+ buried layer (N+BL). Since the Nwell is used as the well to house the vertical NPN transistor as well as the PMOS transistors, any alterations made to this region would affect not only the bipolar devices, but also the CMOS devices. Additional heat cycling would be needed to ensure that the up diffusing N+BL would meet the down-diffusing Nwell. As in the bipolar process, an increase in the lateral diffusion and, hence, design rules for both the existing low voltage bipolar and CMOS components would result.
In a BiCMOS process where it is necessary to increase the voltage of the bipolar devices and remain compatible with the standard cell methodology, this would not be acceptable. The purpose for a standard cell methodology is to decrease design times and increase success. Therefore, the technique for obtaining higher voltage operation must not impact the current low voltage cells, but must still enhance the process to produce higher voltage operation, thus maintaining compatibility with a standard cell methodology. The approach of indiscriminately increasing the epitaxial thickness would be unacceptable when conforming to a standard cell methodology.
Furthermore, in a bipolar process there comes a point at which increasing the epitaxial thickness no longer brings adequate returns in terms of increasing the operating voltage of the transistor. This is referred to as non-thickness limited breakdown between the base and the collector. The technique used to increase the operating voltage or BVceo of this transistor is to increase the epitaxial resistivity. An increase in resistivity, or decrease in doping level, reduces the slope of the electric field within the epitaxial layer, thereby increasing the amount of voltage that can be dropped across a given distance. This reduction in the doping level of the epitaxial layer lowers punchthrough voltages within the silicon, necessitating increased distances between diffusions of the same type. Since in a BiCMOS process the epitaxial layer is used in a different manner (i.e. it forms the isolation between adjacent devices) this approach would not produce the same result. Regardless, if the epitaxial resistivity were changed the same alteration in punchthrough voltages would occur making it a non-viable possibility for standard cell design strategies.